Field of the Invention
The present invention relates to an image forming apparatus which includes a semiconductor disk, a memory management method for the image forming apparatus, and a program.
Description of the Related Art
Conventionally, image forming apparatuses include a hard disk drive (HDD) and a static random access memory (SRAM). The HDD and the SRAM store programs, and realize a storage function for storing image data, performing editing, and managing auxiliary information.
In general, important non-volatile data which is required to be protected even when there is an unexpected power shutdown has been managed in the SRAM. Such non-volatile data stored in the SRAM is divided and classified into regions for each use case, and partial regions are updated according to the respective usages thereof.
It is necessary for each of such regions to be reliable. Further, since each of the regions is frequently updated at high speed, a high-speed SRAM having high reliability and high tolerance with respect to updating is required.
On the other hand, a solid state drive (SSD), which has high-speed performance and high reliability, has become capable of managing non-volatile data, which has been conventionally stored in the SRAM. The SSD is a semiconductor disk, which has rapidly become widely-used in mobile personal computers (PC) due to the increased capacity and lowering of cost.
Further, the SSD can be randomly-accessed at high speed as compared to the HDD. Furthermore, the SSD is of low power consumption, high impact resistance, light weight, and space-saving. In particular, an initial operation such as a spin-up, which is necessary in the HDD when a system is activated, is unnecessary in the SSD. The SSD is thus greatly effective in high-speed data transfer and shortening start-up time, so that it is also gathering attention as a storage device for image forming apparatuses.
However, a response speed of a NAND-type flash memory, which is a storage device included in the SSD, is slow on its own. Further, there is an upper limit on writable frequency of the flash memory (i.e., approximately 100,000 times for a single level cell (SLC) type, and 10,000 times for a multi level cell (MLC) type).
Furthermore, when data previously stored in the NAND-type flash memory is to be deleted, the stored data can be deleted only in units of blocks. As a result, when the stored data is to be rewritten, the following method is performed. The necessary portion of the data to be rewritten is copied in a block other than the original block. Update data is then written in the block other than the original block, and the data in the original block is deleted.
A considerable amount of time is required for rewriting the data according to the above-described method.
To solve such an issue, Japanese Patent Application Laid-Open No. 2002-324008 and Japanese Patent Application Laid-Open No. 2008-097339 discuss the following technique. A flash memory controller included in the SSD causes the block storing the original data and the block for writing the update data to coexist as a pair.
More specifically, the flash memory controller performs the following operation over a plurality of flash memories. The flash memory controller additionally writes in a different block an update portion of rewrite data without changing the data in the original block. When the data is to be read, the flash memory controller merges the contents of both blocks. As a result, the time for reading the regions other than the update portion and the time for merging the read portion with the update portion become unnecessary as compared to rewriting of the data as described above, so that the updating time becomes shortened.
Further, if the block size has become fully-used when the update data is additionally written, it is necessary to write back in the original block all of the update information (i.e., perform pair cancellation) and allocate a different block. In such a case, extra time becomes necessary for allocating a new block with respect to additionally writing the data corresponding to the update portion for evenly distributing the write frequency, so that the updating time becomes longer.
Furthermore, in recent years, there is an increasing demand for security and privacy protection of data stored in a storage device included in image forming apparatuses. Spool data and the stored data recorded in the storage device are thus required to be completely erasable in the flash memory.
To solve such issues, the flash memory controller included in the SSD cancels a difference updating state in the above-described pair, writes back the difference data in the original data, and discards the difference information (i.e., performs a pair cancellation-data deletion process). The pair cancellation-data deletion process is realized by performing a data deletion-writing process in which the data to be deleted becomes completely deleted on the flash memory, as an extended command.
As described above, non-volatile information can be written and read at high speed by accessing the SSD via the controller, which controls a plurality of flash memories as one device.
However, since each region in the SSD is managed in units of blocks, if the above-described SRAM data is arranged in the same size, the divided regions are collectively updated in units of blocks.
In such a case, it becomes necessary for the data included in one block to be updated in a plurality of use cases. The number of updates for each block per unit time thus becomes high, and the above-described pair cancellation process is executed. The pair cancellation process may take 10 to 100 times longer as compared to performing the additional writing process, so that the process time for updating a region suddenly becomes slow.
In particular, when the image forming apparatus executes a print operation, it becomes necessary to perform updating. For example, if there is a sudden delay in writing charging information, the image forming apparatus may become unable to guarantee processing the original number of sheets to be printed per unit time.
In recent years, a solid state drive (SSD) has rapidly become widely-used in mobile personal computers (PC) by achieving higher capacity and lower cost. The SSD can be randomly accessed at high speed as compared to the HDD. Further, the SSD is of low power consumption, high impact resistance, light weight, and space-saving. In particular, an initial operation such as a spin-up, which is necessary in the HDD when a system is activated, is unnecessary in the SSD. The SSD is thus extremely effective in high-speed data transfer and shortening start-up time, so that it is also gathering attention as a storage device for image forming apparatuses.
However, a response speed of a NAND-type flash memory, which is a storage device included in the SSD, is slow on its own. Further, there is an upper limit on writable frequency of the flash memory (i.e., approximately 100,000 times for a single level cell (SLC) type, and 10,000 times for a multi level cell (MLC) type).
Further, there is a decreasing trend in the number of times the flash memory is rewritable from the current number due to processes becoming more fine. In response to such issues, a flash memory controller included in the SSD employs a technique referred to as wear leveling. More specifically, the flash memory controller evenly writes data in different locations so that writing does not become concentrated on the same region, and thus extends a life of the storage device.
Furthermore, when data previously stored in the NAND-type flash memory is to be deleted, the stored data can be deleted only in units of blocks. As a result, when the stored data is to be rewritten, the following method is performed. The necessary portion of the data to be rewritten is copied in a block other than the original block. Update data is then written in the block other than the original block, and the data in the original block is deleted.
However, a considerable amount of time is required for rewriting data according to the above-described method. To solve such an issue, Japanese Patent Application Laid-Open No. 2002-324008 and Japanese Patent Application Laid-Open No. 2008-097339 discuss the following technique. The flash memory controller included in the SSD causes the block storing the original data and the block for writing the update data to coexist as a pair.
More specifically, the flash memory controller performs the following operation over a plurality of flash memories. The flash memory controller additionally writes an update portion of rewrite data in a different block without changing the data in the original block. When the data is to be read, the flash memory controller merges the contents of both blocks.
As a result, the time for reading the regions other than the update portion and the time for merging the read portion with the update portion become unnecessary as compared to rewriting the data as described above. The updating time thus becomes shortened.
Further, if the block size has become fully-used when the update data is to be additionally written, it is necessary to write back in the original block all of the update information (i.e., perform pair cancellation) and allocate a different block. In such a case, extra time becomes necessary for allocating a new block with respect to additionally writing the data corresponding to the update portion for evenly distributing the write frequency, so that the updating time becomes longer.
Furthermore, in recent years, there is an increasing demand for security and privacy protection of the data stored in the storage device included in the image forming apparatus. Spool data and the stored data recorded in the storage device are thus required to be completely erasable in the flash memory.
To solve such issues, the flash memory controller included in the SSD cancels a difference updating state in the above-described pair, writes back the difference data in the original data, and discards the difference information (i.e., performs a pair cancellation-data deletion process). The pair cancellation-data deletion process is realized by performing a data deletion-writing process in which the data to be deleted becomes completely deleted on the flash memory, as an extended command.
As described above, non-volatile information can be written and read at high speed by accessing the SSD via the controller, which controls a plurality of flash memories as one device.
Conventionally, important non-volatile data which is required to be protected even when there is an unexpected power shutdown has been managed in the SRAM. Such non-volatile data stored in the SRAM are generally divided and classified into regions for each use case, and partial regions are updated according to usage thereof.
It is necessary for each of such regions to be reliable. Further, since each of such regions is frequently updated at high speed, a high-speed SRAM having high reliability and high tolerance with respect to updating is required. In contrast, the SSD which has high-speed performance and high reliability has become capable of managing the non-volatile data which has been stored in the SRAM.
However, if the number of times a block is updated in the SSD exceeds a predetermined amount, the above-described pair cancellation process is performed. The pair cancellation process may take 10 to 100 times longer as compared to performing the additional writing process, so that the process time for updating a region suddenly becomes slow. In particular, when the image forming apparatus executes a print operation, it becomes necessary to perform updating. For example, if there is a sudden delay in writing charging information, the image forming apparatus may become unable to guarantee processing the original number of sheets to be printed per unit time.